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note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: mobile phone xenon photoflash capacitor charger with igbt driver a8437 for existing customer transition, and for new customers or new appli- cations, contact allegro sales. date of status change: march 4, 2013 this device is no longer in production. the device should not be purchased for new design applications. samples are no longer available. discontinued product
a8437 description the allegro ? a8437 xenon photoflash charger ic is designed to meet the needs of ultra-low power, small form factor cameras, particularly camera-phones. the charge current time is adjustable by setting the charge current limit from 0.4 to 1.2 a maximum. by using primary- side voltage sensing, the need for a secondary-side resistive voltage divider is eliminated. this has the additional benefit of reducing leakage currents on the secondary side of the transformer. to extend battery life, the a8437 features very low supply current draw?typically 0.1 a in shutdown mode and 10 a in standby mode. the a8437 has a flash dual trigger igbt driver and flash interlock to increase the device noise immunity. the igbt driver also has separate source and sink connections, for flexibility in controlling igbt rise and fall times. the charge and trigger voltage logic thresholds are set at 1.1 v hi (min) to support applications implementing low voltage control logic. the a8437 is available in a 10-pin, 3 mm 3 mm dfn/mlp package with exposed pad for enhanced thermal performance. for an even smaller pcb footprint, a wafer-level chip scale package (wlcsp) option is available. applications include: ? mobile phone flash ? digital and film camera flash a8437-ds, rev. 1 features and benefits ? low quiescent current draw (0.1 a in shutdown mode) ? primary-side output voltage sensing; no resistor divider required ? user-adjustable current limit from 0.4 to 1.2 a ? 1.1 v logic (v hi (min)) compatibility ? integrated igbt driver with separate sink and source (cg package) or common sink/source (ej package) ? flash dual trigger with interlock for increased noise immunity ? optimized for mobile phone, 1-cell li+ battery applications ? no primary-side schottky diode needed ? zero-voltage switching for lower loss ? >75% efficiency ? optional regulation feature to maintain the output voltage ? charge complete indication ? integrated 40 v dmos switch mobile phone xenon photoflash capacitor charger with igbt driver packages: typical application application 1. typical application without output voltage regulation. note: application must periodically restart the charging cycle to recover lost charge on the output capacitor. + sw 1 : 10 iset vin control block charge done gnd gsource trigger1 igbt driver igbt gate gsink vpullup reg connect to vin vout detect i sw sense done rset battery input 2.3 to 5.5 v c2 cout 100 f 315 v c1 100 k tlim trigger2 12-ball wlcsp 1.205 mm 1.635 mm 0.5 nominal overall height (package cg) + sw 1 : 10 iset vin control block charge done gnd trigger1 vin igbt driver igbt gate gate vpullup trigger2 reg connect to vin vout detect done rset c2 cout 100 f 315 v c1 100 k i sw sense battery input 2.3 to 5.5 v cg package ej package 10-contact dfn/mlp 3 mm 3 mm 0.75 nominal overall height (package ej)
mobile phone xenon photoflash capacitor charger with igbt driver a8437 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number package packing A8437ECGLT * 12-ball wlcsp tape and reel, 4000 pieces per reel a8437eejtr-t 10-contact dfn/mlp tape and reel, 1500 pieces per reel *contact allegro for additional ordering information. thermal characteristics characteristic symbol test conditions 1 value units package thermal resistance 2 r ja cg package, on 4-layer pcb based on jedec standard 100 oc/w ej package, on 2-layer pcb with 0.88 in. 2 area of 2 oz. copper each side, based on jedec standard 65 oc/w ej package, on 4-layer pcb based on jedec standard 45 oc/w 1 additional thermal information available on allegro website. 2 cg results preliminary. absolute maximum ratings characteristic symbol notes rating units sw pin v sw dc voltage. (v sw is self-clamped by internal active clamp and is allowed to exceed 40 v during flyback spike durations. maximum repetitive energy during flyback spike: 0.5 j at frequency 400 khz.) ?0.3 to 40 v vin pin v in ?0.3 to 6.0 v charge, trigger x , d o n e pins care should be taken to limit the current when ?0.6 v is applied to these pins. ?0.6 to v in + 0.3 v v remaining pins ?0.3 to v in + 0.3 v v operating ambient temperature t a range e ?40 to 85 oc maximum junction t j (max) 150 oc storage temperature t stg ?55 to 150 oc
mobile phone xenon photoflash capacitor charger with igbt driver a8437 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vin sw gnd ocp iset reg charge 0.96 v 1.2 v v ds ref t on (max) t off (max) done gate ej package cg package v in v in trigger1 trigger2 dmos v sw ? v bat q q s r q q s r dcm detector iset buffer h m l triggered timer control logic 18 s 18 s enable gnd gsource gsink
mobile phone xenon photoflash capacitor charger with igbt driver a8437 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com name number function cg ej iset c4 1 sets the maximum switch current; connect an external resistor to gnd to set the desired peak current gate ? 2 igbt gate drive ? sink/source gsource b3 ? igbt gate drive ? source gsink c3 ? igbt gate drive ? sink vin c2 3 input voltage; connect to a 2.3 to 5.5 v bias supply gnd c1 4 ground connection charge b1 5 pull high to initiate charging; pull low to enter low-power standby mode trigger2 b2 6 igbt input trigger 2 sw a1 7 drain connection of internal power mosfet switch; connect to transformer trigger1 a2 8 igbt input trigger 1 d o n e a3 9 pulls low when output reaches target value and charge pin is high; goes high dur- ing charging or whenever charge pin is low tlim a4 ? for production test only; connect to gnd on pcb reg b4 10 output voltage regulation pin; connect to external resistor and capacitor to regulate output voltage, or connect to vin pin to disable regulation (see output regulation section for details) ep n.a. ? exposed pad for enhanced thermal dissipation; not connected electrically terminal list table (contacts down views) 10 9 8 7 6 1 2 3 4 5 reg done trigger1 sw trigger2 iset gate vin gnd charge ep pin-out diagrams cg package ej package orientation mark on ball side a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c4
mobile phone xenon photoflash capacitor charger with igbt driver a8437 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics typical values valid at v in = 3.6 v, r set = 33 k , i swlim = 1.0 a, and t a =25c, unless otherwise noted characteristics symbol test conditions min. typ. max. unit vin voltage range v in 2.3 ? 5.5 v uvlo enable threshold v inuv v in rising ? 2.05 2.2 v uvlo hysteresis v inuvhys ? 150 ? mv vin supply current i in shutdown (charge = 0 v, trigger1 and trigger2 = 0 v) ? 0.01 0.5 a charging complete, regulation disabled (reg = vin) ? 10 50 a charging complete, regulation enabled ? 0.5 ? ma charging (charge = vin, trigger1 and trigger2 = 0 v) ?2 ?ma current limits switch current limit 1 i swlimmax maximum, r set = 26.7 k 1.08 1.2 1.32 a i swlimmin minimum, r set = 85 k ? 0.4 ? a sw / iset current ratio i sw /i set r set = 33 k , charge = high ? 28 ? ka/a iset pin voltage while charging v set r set = 33 k , charge = high ? 1.2 ? v iset pin internal resistance r set(int) ? 1000 ? switch on-resistance r swds(on) v in = 3.6 v, i d = 800 ma, t a = 25c ? 0.25 ? switch leakage current 2 i swlk v sw = v in (max), over temperature range ? ? 2 a combined v in and sw leakage current at t a =25c v in = 5.5 v in shutdown ? ? 0.5 a charge input current i charge v charge = v in ? 36 ? a charge input voltage 2 v charge high, over input supply range 1.1 ? ? v low, over input supply range ? ? 0.4 v charge pull-down resistor value r chpd ? 100 ? k charge on/off delay t ch ? 20 ? us maximum switch-off timeout t offmax ? 18 ? s maximum switch-on timeout t onmax ? 18 ? s d o n e output leakage current 2 i donelk ??1 a d o n e output low voltage 2 v donel 32 a into d o n e pin ? ? 100 mv output comparator trip voltage 2 v outtrip measured as v sw ? v in 31 31.5 32 v output comparator overdrive v outov pulse width = 200 ns (90% to 90%) ? 200 400 mv minimum dv/dt for zvs comparator dv/dt measured at sw pin ? 20 ? v/ s regulation reg voltage when charging completes v reg(h) charge = high, at d o n e low transition 1.15 1.2 1.25 v reg voltage threshold for regulation v reg(l) charge = high, at d o n e = low ? 0.96 ? v reg output current drive capability i reg charge = high, at d o n e = high, v sw ? v in = 30 v, v reg = 1.0 v ? 50 ? a reg leakage current while not charging i reglk charge = high, at d o n e = low, v reg = 1.2 v ? 0.1 ? a igbt driver trigger, trigger2 input voltage 2 v trig(h) input = logic high, over input supply range 1.1 ? ? v v trig(l) input = logic low, over input supply range ? ? 0.4 v trigger, trigger2 pull-down resistor r trigpd ? 100 ? k gsource resistance to vin 3 r srcds(on) v in = 3.6 v, v gsource =1.8 v ? 5 ? gsink resistance to gnd 3 r snkds(on) v in = 3.6 v, v gsink = 1.8 v ? 6 ? propagation delay (rising) t dr gsource and gsink tied together, measurement taken at pin; r gate = 12 , c l = 6500 pf, v in = 3.6 v ?30?ns propagation delay (falling) t df ?30?ns output rise time t r ?70?ns output fall time t f ?70?ns 1 current limit guaranteed by design and correlation to static test. refer to application section for peak current in actual circ uits. 2 specifications over the range t a = ?40c to 85c; guaranteed by design and characterization. 3 gsource and gsink tied together (gate pin) in ej package.
mobile phone xenon photoflash capacitor charger with igbt driver a8437 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the two trigger signals are internally anded together. as shown in the timing diagram, below, triggering is prohibited dur- ing the initial charging process. this prevents premature firing of the flash before the output capacitor has been charged to its target voltage. refer to the section igbt gate driver interlock for details. timing and igbt interlock function v out charge vin trigger igbtdrv sw done a b c d case description a trigger pulse arrives before first charging process is finished (charge and d o n e pins are both high). igbtdrv is disabled in this case. b arrives during regulation mode, while not refreshing. igbtdrv is enabled. charging resumes once trigger is low again. c arrives during regulation mode, while refreshing. charging is stopped after present cycle. igbtdrv is enabled. charging resumes after trigger is low again. d arrives while ic is in low-power standby mode (charge pin is low). igbtdrv is always enabled in this case. igbt drive timing definition gsource, gsink, or gate trigger t dr t r t df t f 50% 10% 90% 50% 10% 90%
mobile phone xenon photoflash capacitor charger with igbt driver a8437 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com performance characteristics charging time at various peak current levels common parameters symbol parameter units/division c1 v out 50 v c2 v bat 1 v c3 i in 100 ma t time 200 ms conditions parameter value v batt 3.6 v c out 20 f t c1 c2 c3 conditions parameter value r set 39 k i swlim 0.9 a i in v out v bat t conditions parameter value r set 33.2 k i swlim 1.0 a i in v out v bat c1 c2 c3 t i in v out conditions parameter value r set 26.7 k i swlim 1.2 a v bat c1 c2 c3 c1 c2 c3 c1 c2 c3 c1 c2 c3
mobile phone xenon photoflash capacitor charger with igbt driver a8437 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com charge time versus battery voltage transformer l p = 8 h, n = 10.2; c out = 20 f / 330 v ucc; t a =25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v bat (v) time (s) 55 0.65 45 0.8 39 0.9 33.2 1.0 26.7 1.2 r set (k ) i p (a) c out = 20 f. for larger or smaller capacitances, charging time scales proportionally. efficiency versus battery voltage 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2.02.53.03.54.04.55.05.56.0 v bat (v) efficiency (%) transformer l p = 8 h, n = 10.2; c out = 20 f / 330 v ucc; t a =25 55 0.65 45 0.8 39 0.9 33.2 1.0 26.7 1.2 r set (k ) i p (a) special low-profile transformer with relatively low inductance (lp= 8 h) and high winding resistance (rp = 0.37 ). higher efficien- cy can be achieved by using transformers with higher lp, which reduces switching frequency and therefore switching loses, and lower resistance, which reduces conduction losses. 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v bat (v) i in (a) average input current versus battery voltage xfm l p = 8 h, n = 10.2, c out = 20 f 330 v ucc, t a =25 55 0.65 r set (k ) i p (a) 45 0.8 39 0.9 33.2 1.0 26.7 1.2 an increase in i swlim with respect to v bat actually keeps the average input current roughly constant throughout the battery voltage range. normally, if i swlim is kept constant, the average current will drop as v bat goes higher.
mobile phone xenon photoflash capacitor charger with igbt driver a8437 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com general operation overview the charge pin enables the part and starts charging. the d o n e open-drain indicator is pulled low when charge is high and target output voltage is reached. charging is reinitiated when the reg pin voltage falls below the regulation threshold. pulling the charge pin low stops charging and forces the chip into low- power standby mode. output voltage regulation when the reg pin is connected to vin, the a8437 stops charging the output voltage after the reflected voltage (v sw ? v in ) reaches 31.5 v. in this mode, charging can be reinitiated by cycling the charge signal through a low to high transition. the a8437 can also be used to regulate output voltage within a predetermined window. in this mode, con- nect a capacitor, creg, and resistor, rreg, from the reg pin to gnd (refer to the figure application 3). when charge is held high, the voltage monitoring circuit of the a8437 is always active, irrespective of the reg pin voltage level. voltage regulation using predicitive droop the a8437 uses a technique called predictive droop for regulat- ing the output capacitor voltage after the completion of a charging cycle. when the target output voltage is reached, the converter stops charging and output capacitor voltage droops due to leakage current. an external resistor and capacitor connected from the reg pin to ground will provide an rc discharge time constant. this time constant can be selected to mirror the droop rate of the output capacitor. when voltage at the reg pin drops to 80% of the reference value, the converter starts charging again and brings the output capacitor back to target voltage again. the time required for an rc network to discharge from v 0 to v t is given by: t = r c ln ( v 0 / v t ) . (1) for example, if c = 10 f, r = 10 m and v 0 / v t = 1.25, then t = 22 seconds. assuming that the rc-dis- charge characteristic of the output capacitor matches that at the reg pin, we can predict that the output voltage has drooped 20%, and therefore it is time to recharge the output capacitor. by implementing a predictive droop technique, no additional leakage paths are introduced on the second- ary side, which helps to keep power losses to a mini- mum. by intentionally making the rc discharge time constant of the reg pin shorter than that of the output capacitor, we can regulate the output voltage to a win- dow tighter than the default 20% hysteresis. voltage regulation using direct sensing if direct sens- ing from the secondary side is desired, connect the reg pin to a resistor divider network across the out- put capacitor to enable output regulation. in this case, the charging cut-off is still controlled by primary side sensing (charging stops when reflected voltage reaches 31.5 v), but the regulation threshold is controlled by the secondary side sensing. when the charge pin is high, and the sensed output voltage falls below the lower v reg threshold, the flyback converter charges the output capacitor again until the primary side sens- ing stops further charging. this cycle repeats till the charge pin is pulled low. the benefit of this method is that a lower output volt- age can be selected independently, simply by chang- ing the resistor divider ratio. for example, given r 1 =10 m , r 2 = 33.2 k , and v reg(l) = 0.96 v, then: v out (low) = v reg(l) ( r 1 / r 2 + 1) = 290 v . (2) selection of switching current limit the a8437 features continuously adjustable peak switching current between 0.4 and 1.2a. this is done application information
mobile phone xenon photoflash capacitor charger with igbt driver a8437 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com by selecting the value of an external resistor rset, connected from the iset pin to gnd, which deter- mines the iset bias current, and therefore the switch- ing current limit, i swlim . to the first order approximation, i swlim is related to i set and r set according to the following equations: i swlim = i set k = v set / r set k , (3) where k = 28000 when battery voltage is 3.6 v. in real applications, the actual switching current limit is affected by input battery voltage, and also the transformer primary inductance, lp. if necessary, the following expressions can be used to determine i swlim more accurately: i set = v set / ( r set + r set(int) ? k r gnd(int) ), (4) where: r set(int) is the internal resistance of the i set pin (1 k typical), r gnd(int) is the internal resistance of the bonding wire for the gnd pin (27 m typical), and k = (k + v in k ), with k = 24350 and k 1040 at t a = 25c. then, i swlim = i set k + v bat / l p t d , (5) where t d is the delay in sw turn-off (0.1 s typical). the chart at the bottom of the page can be used to determine the relationship between r set and i swlim at various battery voltages. peak current limit versus iset resistance v in = v bat , xfm lp = 8 h, t a =25c 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 25 30 35 40 45 50 55 60 65 70 75 80 85 90 r set (k ) i swlim (a) v in = 5.5 v v in = 4.5 v v in = 3.6 v v in = 3.0 v v in = 2.3 v
mobile phone xenon photoflash capacitor charger with igbt driver a8437 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com smart current limit (optional) with the help of some simple external logic, the user can change the charging current according to the battery voltage. for example, assume that i set is normally 36 a (for i swlim = 1.0 a). referring to the following illustration, when the battery voltage drops rset iset bl rbl below 2.5 v, the signal at bl (battery-low) goes high. the resistor rbl, connecting bl to the iset pin, then injects 10 a into rset. this effectively reduces iset current to 26 a (for i swlim = 0.73 a). a disad- vantage of the above method is that the 10 a current is always flowing whenever the bl signal goes high. timer mode and fast charging mode the a8437 achieves fast charging times and high effi- ciency by operating in discontinuous conduction mode (dcm) through most of the charging process. the relationship of timer mode and fast charging mode is shown in the following figure. timer mode fast charging mode i in v bat v out t =200 ms/div; v out =50 v/div; v bat =1 v/div.; i in =100 ma/div. v bat =3.6 v; c out =20 f/330 v; r set =46 k (i swlim 0.75 a) the ic operates in timer mode when beginning to charge a completely discharged photoflash capaci- tor, usually when the output voltage, v out , is less than approximately 15 to 20 v. timer mode is a fixed period, 18 s, off-time control. one advantage of having timer mode is that it limits the initial battery current surge and thus acts as a ?soft-start.? a time- expanded view of a timer mode interval is shown in the following figure. i sw v bat v out v sw v out 14 v; t =2 s/div; v bat =3.6 v; r set =33.2 k as soon as a sufficient voltage has built up at the output capacitor, the ic enters fast-charging mode. in this mode, the next switching cycle starts after the secondary side current has stopped flowing, and the switch voltage has dropped to a minimum value. a proprietary circuit is used to allow minimum-voltage switching, even if the sw pin voltage does not drop to 0 v. this enables fast-charging mode to start earlier than previously possible, thereby reducing the overall charging time. minimum-voltage switching is shown in the following figure. i sw v bat v out v sw v out 15 v; t =1 s/div; v bat =3.6 v; r set =33.2 k during fast-charging mode, when v out is high enough (over 50 v), true zero-voltage switching timer mode minimum voltage switching
mobile phone xenon photoflash capacitor charger with igbt driver a8437 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com (zvs) is achieved. this further improves efficiency as well as reduces switching noise. a zvs interval is shown in the following figure. i sw v bat v out v sw i sw v bat v out v sw v out = 120 v; t =0.2 s/div; v bat =3.6 v; r set =33.2 k igbt gate driver interlock the trigger1and trigger2 pins are anded together inside the ic to control the igbt gate driver. if only one trigger signal is needed, tie both trigger pins together and use as a single input. triggering is disabled (locked) during charging. this is to prevent switching noise from interfering with the igbt driver. after the charge pin goes high (at the start of a charging cycle), the ic must wait for comple- tion of the charging cycle (d o n e goes low) before triggering can be enabled, according to the following chart: conditions resulting state charge d o n e igbt gate driver low don?t care enabled high high disabled high low enabled after completion of the charging cycle, if the charge pin is kept high and reg is enabled, the ic will periodically recharge the output. if a trigger signal comes in during a recharge cycle, charging will be halted immediately and the igbt gate driver will be allowed to fire after a delay of less than 1 s. charging resumes after the trigger signal is removed. red eye reduction the igbt gate driver is always enabled when charge is low. if the charge pin is disabled before sufficient voltage has built up on the output capacitor, the flash may not fire. in the case of red-eye reduction flashes, it is recommended to keep the charge pin low until completion of triggering pulses. this ensures that the igbt gate driver will remain enabled regard- less of the d o n e state. zero voltage switching
mobile phone xenon photoflash capacitor charger with igbt driver a8437 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ambient light sensing ambient light sensing (als) can be easily imple- mented for the a8437 using the trigger2 pin plus three external components. this configuration is shown in the figure below. the phototransistor current is proportional to the intensity of the light that it receives. when there is sufficient ambient light (for example, during daylight outdoor photographing), a current of about 30 a can flow through the phototransistor. this forces the voltage at trigger2 pin to fall to 0.8 v or lower, so it prohibits trigger1 from firing the flash. the exact threshold of ambient light required to prohibit flash firing can be adjusted by r tgr1 . the smaller this resistance, the brighter the ambient light must be to prohibit flash firing. when ambient conditions are dark, the current flow- ing through the phototransistor is in less than 1 a. because the trigger2 pin is biased at 1.4 v or + sw 1 : 10 iset vin control block tlim charge done gnd gsource trigger1 vin igbt driver igbt gate gsink trigger2 reg connect to vin vout detect isw sense done rset battery input 2.3 to 5.5 v bias voltage 2.5 to 5.5 v c2 cout 100 f 315 v c1 a a r tgr1 100 k pnz121s phototransistor it is recommend to use a regulated system voltage for the bias. if battery voltage is used, the als sensitivity will vary with battery voltage, and there would be a small leakage current even when the camera is turned off. c tgr1 1 f als typical application (cg package shown)
mobile phone xenon photoflash capacitor charger with igbt driver a8437 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com higher, trigger1 is allowed to activate the igbt gate driver (and thereby fire the flash). the capacitor ctgr1 and resistor rtgr1 form an integrator for light exposure. when the flash fires, bright light bounces back from subject and enters the phototransistor. in example a below, the flash termi- nates after just 30 s, without fully discharging the photoflash capacitor. if the subject is far away, the reflected light intensity is lower, so the phototransistor current is also lower. in example b below, the flash stays on for longer time (60 s) and discharges more energy from the photo- flash capacitor. using a larger c tgr1 causes the time constant of the integrator to increase, so a longer pulse is required before the flash is terminated. example a example b common parameters symbol parameter units/division c1 v out 50 v c2 v trigger2 1 v c3 v trigger1 5 v c4 v gate 5 v t time 20 s c1 c4 c4 c2 c3 c1 t v gate v out v trigger2 v trigger1 c2 c3 c1 c4 c4 c2 c3 c1 t v gate v out v trigger2 v trigger1 c2 c3
mobile phone xenon photoflash capacitor charger with igbt driver a8437 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com transformer selection 1. the transformer turns ratio, n, determines the out- put voltage: n = n s / n p v out = 31.5 n ? v d , where 31.5 is the typical value of v outtrip , and v d is the forward drop of the output diode. 2. the primary inductance, l p , determines the on-time of the switch: t on = (? l p / r ) ln (1 ? i swlim r / v in ) , where r is the total resistance in the primary current path (including r swds(on) and the dc resistance of the transformer). if v in is much larger than i swlim r, then t on can be approximated by: t on = i swlim l p / v in . 3. the secondary inductance, l s , determines the off- time of the switch. given: l s / l p = n n , then t off = ( i swlim / n ) l s / v out = ( i swlim l p n ) / v out . the minimum pulse width for t off determines what is the minimum l p required for the transformer. for example, if i swlim = 0.7 a, n = 10, and v out = 315 v, then l p must be at least 9 h in order to keep t off at 200 ns or longer. these relationships are illustrated in the figure at the bottom of the page. in general, choosing a transformer with a larger l p results in higher efficiency (because a larger l p means lower switch frequency and hence lower switching loss). but transformers with a larger l p also require more windings and larger magnetic cores. therefore, a trade-off must be made between transformer size and efficiency. component selection selection of the flyback transformer should be based on the peak current, according to the following table: i peak range (a) supplier part number l p ( h) 0.4 to 1.0 tdk ldt565630t-002 14.5 0.6 to 1.2 tdk ldt565630t-003 10.5 0.75 to 1.0 tdk ldt565620st-203 8.2 v sw v sw v in v in i sw i sw t on t off v r t f t neg
mobile phone xenon photoflash capacitor charger with igbt driver a8437 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application 2. maintaining output target voltage by directly monitoring the output voltage (reg pin connected to a secondary-side resistor divider). cg package shown. + sw battery input 2.3 to 5.5 v c2 cout 100 f 315 v 1 : 10 c1 iset vin control block tlim charge done gnd 100 k gsource trigger1 vin igbt driver igbt gate gsink vpullup trigger2 reg vout detect isw sense done rset 10 m 38.3 k application 3. maintaining output voltage by predicting the output voltage droop (reg pin connected to primary-side rc network). cg package shown. + sw battery input 2.3 to 5.5 v c2 cout 100 f 315 v 1 : 10 c1 c reg r reg 10 m f iset vin control block tlim charge done gnd 100 k gsource trigger1 vin igbt driver igbt gate gsink vpullup trigger2 reg vout detect isw sense done rset 10 m c r e g r re g 10 m f 1 0 m
mobile phone xenon photoflash capacitor charger with igbt driver a8437 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package cg, 12-ball wlcsp ? 0.19 0.2225 0.208 x ? .17 1.215 1.645 0.550 max 0.400 1.200 0.40 0.800 1234 0.40 a b c c b a 1234 a b c 1234 a all dimensions nominal, not for tooling use dimensions in millimeters dimensions exclusive of burrs exact configuration at supplier discretion within limits shown a terminal #a1 mark area b b reference pad layout; all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances pcb layout reference view seating plane c die orientation mark c 0.05 12x c c
mobile phone xenon photoflash capacitor charger with igbt driver a8437 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ej, 3 mm x 3 mm 10-contact dfn/mlp 2.38 10 10 2 1 2 1 a a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-229weed) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 son50p300x300x80-11weed3m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) b pcb layout reference view 1.64 2.38 0.30 1 10 0.50 0.85 3.10 c 1.64 c 0.08 11x c seating plane d 0.25 +0.05 ?0.07 0.50 0.75 0.05 3.00 0.15 3.00 0.15 0.40 0.10
mobile phone xenon photoflash capacitor charger with igbt driver a8437 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com cg package marking line 1: bump a1 mark nn ? last two digits of the device number (37) n n y w w line 2: date code y ? last digit of year of manufacture ww ? week of manufacture (marks on substrate side, exact appearance at supplier discretion)
mobile phone xenon photoflash capacitor charger with igbt driver a8437 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical reflow profile per j-std-020d ipc-020d-5-1 jstd020d-01, figure 5-1 classi cation pro le (not to scale) t c -5c t max. ramp up rate = 3c/s max. ramp down rate = 6c/s preheat area t smax t smin t s t p t l temperature time 25 time 25c to peak supplier t p > t c - supplier t p t c user t p < t c - user t p t c -5c t p l
mobile phone xenon photoflash capacitor charger with igbt driver a8437 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2006-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. typical reflow profile per j-std-020d jstd020d-01 table 5-2 classi cation re ow pro les y l b m e s s a e e r f - b p y l b m e s s a c i t c e t u e b p - n s e r u t a e f e l o r p preheat/soak temperature min (t smin ) temperature max (t smax ) time (t s )from(t smin to t smax ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds ramp-up rate (t l to t p . x a m d n o c e s / c 3 . x a m d n o c e s / c 3 ) liquidous temperature (t l ) time (t l ) maintained above t l 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p ) for users t p must not exceed the classi cation temp in table 4-1. for suppliers t p must equal or exceed the classi cation temp in table 4-1. for users t p must not exceed the classi cation temp in table 4-2. for suppliers t p must equal or exceed the classi cation temp in table 4-2. time (t p )* within 5 c of the speci ed classi cation temperature (t c ), see figure 5-1. s d n o c e s * 0 3 s d n o c e s * 0 2 ramp-down rate (t p to t l . x a m d n o c e s / c 6 . x a m d n o c e s / c 6 ) . x a m s e t u n i m 8 . x a m s e t u n i m 6 e r u t a r e p m e t k a e p o t c 5 2 e m i t * tolerance for peak pro le temperature (t p )isde ned as a supplier minimum and a user maximum. note 1: all temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly re ow (e.g., live-bug). if parts are re owed in other than the normal live-bug assembly re ow orientation (i.e., dead-bug), t p shall be within 2 c of the live-bug t p and still meet the t c requirements, otherwise, the pro le shall be adjusted to achieve the latter. to accurately measure actual peak package body temperatures refer to jep140 for recommended thermocouple use. note 2: re ow pro les in this document are for classi cation/preconditioning and are not meant to specify board assembly pro les. actual board assembly pro les should be developed based on speci c process needs and board designs and should not exceed the parameters in table 5-2. for example, if t c is 260 c and time t p is 30 seconds, this means the following for the supplier and the user. for a supplier: the peak temperature must be at least 260 c. the time above 255 c must be at least 30 seconds. for a user: the peak temperature must not exceed 260 c. the time above 255 c must not exceed 30 seconds. note 3: all components in the test load shall meet the classi cation pro le requirements. note 4: smd packages classi ed to a given moisture sensitivity level by using procedures or criteria de ned within any previous version of j-std-020, jesd22-a112 (rescinded), ipc-sm-786 (rescinded) do not need to be reclassi ed to the current revision unless a change in classi cation level or a higher peak classi cation temperature is desired.

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